Đề tài A soft error tolerant sram design in 130nm cmos technology - Lê Thị Linh An

VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY UNIVERSITY OF SCIENCE LÊ THỊ LINH AN A SOFT ERROR TOLERANT SRAM DESIGN IN 130NM CMOS TECHNOLOGY Specialization: Electronic Engineering – Microelectronics Major Code: 60 52 70 MASTER DEGREE THESIS ELECTRONICS ENGINEERING – MICROELECTRONICS SUPERVISOR Dr. BÙI TRỌNG TÚ Ho Chi Minh City, 2010 ACKNOWLEDGEMENTS It is my pleasure to thank all the people who made this thesis possible. First of all, I would like to sincerely express my appreciation to my advisor, Dr. Bui Trong Tu, for his tremendous support, valuable guidance and constant encouragement during my studies. His technical advice made my master’s studies a meaningful learning experience. I am also grateful to Prof. Dang Luong Mo, Prof. Nguyen Huu Phuong, and Dr. Huynh Huu Thuan, who are the managers of this Microelectronics Master program. This is really an interesting course with enthusiastic and devoted professors, who are the experts in the IC industry. I also wish to thank my colleagues in TCAM team for all helpful discussion and valuable advice during my study. Appreciation is expressed for Silicon Design Solutions Company who have supported me about financial and let me join in this Master course during my work. Finally, my special thanks to my family who have always been with me throughout the difficulties and challenges of my master study. Ho Chi Minh City, November 2010 Le Thi LinhAn ABSTRACT Soft error is a great concern for microelectronics circuits today. With the advanced development in CMOS technologies, VLSI circuits are becoming more sensitive to external noise sources, especially radiation particle strikes, which are the cause of soft error. Soft errors are random and do not cause the permanent failure. However, it causes the corruption of stored information, which could turn to the failure in functionality of the circuits. Meanwhile, the demand for a higher reliability of electronics applications is always a non-stop requirement. There are a lot of critical applications that need the extreme exactly in circuit functionality, such as the circuits used in space or biomedical equipment, as well as the military electronics and so on. Generally, soft errors in memories attracted more attention than soft errors in logic circuit. In addition, memories play an important part in modern system. Because of the high integration of storage cells, a large memory is more sensitive to particle strikes than logic. Due to that motivation, this thesis focuses to study about soft errors in memories. The thesis goes through the background knowledge of soft errors and its mitigation techniques. Then, a SRAM design with additional soft error tolerant feature will be presented. The SRAM is designed in 130nm CMOS technology, using circuit hardening and error correcting code techniques to mitigate the soft error effect. The soft error tolerant level is verified by some simulations. Not only focus on the soft error tolerant circuits, a whole SRAM architecture will be shown in detail, from circuit to physical implementation. The verification and simulation results are also included. TABLE OF CONTENTS Acknowledgement Abstract Table of contents Abbreviations List of tables List of figures CHAPTER 1 - INTRODUCTION .................................................................................... 1 1.1. Problem and motivation ............................................................................................. 1 1.2. Contribution of the thesis ........................................................................................... 2 1.3. Thesis organization .................................................................................................... 2 CHAPTER 2 - BACKGROUND ....................................................................................... 4 2.1. Soft errors in semiconductor device ........................................................................... 4 2.1.1. Radiation sources ................................................................................................. 4 2.2. Soft errors occurrence mechanism ............................................................................. 5 2.3. Soft errors mitigation techniques ............................................................................... 6 2.3.1. Device level techniques ....................................................................................... 6 2.3.2. Circuit level techniques ....................................................................................... 7 2.3.3. Block level techniques ......................................................................................... 7 CHAPTER 3 – SOFT ERROR TOLERANT SRAM DESIGN ................................... 10 3.1. SRAM specification ................................................................................................. 10 3.1.1. General information ........................................................................................... 10 3.1.2. Floorplan ............................................................................................................ 11 3.1.4. Operation brief description ................................................................................ 12 3.2. SRAM detail design ................................................................................................. 14 3.2.1. SRAM cell architecture ..................................................................................... 14 3.2.2. Replica path for Read operation ........................................................................ 15 3.2.3. Internal clock generator ..................................................................................... 17 3.2.4. Write circuit ....................................................................................................... 19 3.2.5. Decoder .............................................................................................................. 19 3.2.6. Input/output latches .......................................................................................... 21 3.3. Error detecting and correcting (EDC) block ............................................................ 22 3.3.1. Hamming code algorithm .................................................................................. 23 3.3.2. EDC block implementation ............................................................................... 24 3.3.3. EDC detail architecture ...................................................................................... 26 CHAPTER 4 – DESIGN SIMULATION AND VERIFICATION .............................. 37 4.1. SRAM cell simulation .............................................................................................. 37 4.1.1. SRAM cell simulation to find device size ......................................................... 37 4.1.2. SRAM cell characteristic summary ................................................................... 42 4.1.3. Static noise margin comparison ......................................................................... 43 4.1.4. SRAM cell capacitance ...................................................................................... 43 4.2. Soft error tolerant simulation ................................................................................... 44 4.2.1. Verification methodology .................................................................................. 44 4.2.2. Critical charge simulation .................................................................................. 45 4.2.3. Simulation results .............................................................................................. 46 4.2.4. Conclusion ......................................................................................................... 49 4.3. Post-layout simulation .............................................................................................. 50 4.3.1. Simulation setup ................................................................................................ 50 4.3.2. Cycle time definition and simulation result ....................................................... 52 4.3.3. Access time ........................................................................................................ 55 4.3.4. Setup time .......................................................................................................... 56 4.3.5. Timing delay of some critical paths................................................................... 57 4.3.6. Simulation results summary .............................................................................. 61 4.4. SRAM and EDC functional verification .................................................................. 61 4.4.3. Simulation setup ................................................................................................ 65 4.4.4. Functional verification result ............................................................................. 67 4.5. Physical verification ................................................................................................. 70 CHAPTER 5 – CONCLUSION AND FUTURE WORK ............................................. 75 ABBREVIATIONS VLSI Very large scale integration CMOS Complementary Metal-Oxide Semiconductor SEU Single Event Upset DRC Design Rule Check LVS Layout versus Schematic SRAM Static Random Access Memory ECC Error Correcting Code EDC Error Detecting and Correcting SNM Static noise margin LPE Layout Parasitic Extraction LIST OF TABLES Table 3.1: Pin description ................................................................................................... 12 Table 3.2: Hamming code for 22 bits ................................................................................. 24 Table 4.1: Read current ...................................................................................................... 38 Table 4.2: Read leakage current ......................................................................................... 38 Table 4.3: Effect of leakage on read current ...................................................................... 38 Table 4.4: Write current ..................................................................................................... 40 Table 4.5: Static noise margin ............................................................................................ 41 Table 4.6: SRAM cell characteristic summary .................................................................. 43 Table 4.7: SNM comparison ............................................................................................... 43 Table 4. 8: SRAM cell capacitance .................................................................................... 44 Table 4.9: Critical charge result of hardened SRAM cell .................................................. 46 Table 4.10: Critical charge result for normal SRAM cell .................................................. 48 Table 4.11: Performance result (SS_125_1.35) ................................................................. 61 Table 4.12: Timing delay between nodes ........................................................................... 61 Table 4.13: Design fault model .......................................................................................... 62 LIST OF FIGURES Figure 2.1: Redundancy ........................................................................................................ 8 Figure 2.2: Concurrent error detection ................................................................................. 8 Figure 3.1: SRAM floorplan ............................................................................................... 11 Figure 3.2: Write operation ................................................................................................ 13 Figure 3.3: Read operation ................................................................................................. 13 Figure 3.4: SRAM cell architecture .................................................................................... 15 Figure 3.5: Timing scheme for read operation ................................................................... 16 Figure 3.6: Reference IO cell and read circuit ................................................................... 17 Figure 3.7: Read clock generator circuit ............................................................................ 18 Figure 3.8: Write clock generator ....................................................................................... 19 Figure 3.9: Write circuit and sequential waveform ............................................................ 19 Figure 3.10: Row decoder block diagram .......................................................................... 20 Figure 3.11: Xdec circuit .................................................................................................... 21 Figure 3.12: Hardened latch architecture ........................................................................... 22 Figure 3.13: EDC block diagram ........................................................................................ 25 Figure 3.14: Write encoder schematic ................................................................................ 27 Figure 3.15: Parity comparison schematic ......................................................................... 28 Figure 3.16: Syndrome decoder schematic ........................................................................ 29 Figure 3.17: Bit flipper block ............................................................................................. 30 Figure 3.18: Input select ..................................................................................................... 31 Figure 3.19: Output select and output latch........................................................................ 32 Figure 3.20: Top level layout view ..................................................................................... 33 Figure 3.21: SRAM cell layout with only device layers shown ......................................... 34 Figure 3.23: Xdec cell layout ............................................................................................. 34 Figure 3.22: SRAM cell layout .......................................................................................... 34 Figure 3.24: Xdec array 1x256 ........................................................................................... 35 Figure 3.25: Control block .............................................................................................. 35 Figure 3.26: IO array 1x22 ................................................................................................. 36 Figure 4.1: Read current ..................................................................................................... 37 Figure 4.2: Write current .................................................................................................... 39 Figure 4.3: Inject a current source to an off NMOS drain ................................................. 45 Figure 4.4: The injected SEU current for hardened SRAM cell ........................................ 47 Figure 4.5: IBL waveform of hardened SRAM cell ........................................................... 47 Figure 4.6: The exchange state between IBL and IBLX .................................................... 47 Figure 4.7: The injected SEU current for normal SRAM cell............................................ 48 Figure 4.8: IBL waveform of normal SRAM cell .............................................................. 48 Figure 4.9: The exchange state between IBL and IBLX .................................................... 49 Figure 4.10: A part of LPE netlist containing capacitance value ....................................... 50 Figure 4.11: A part of LPE netlist containing resistor value .............................................. 51 Figure 4.12: A part of input waveform for performance simulation .................................. 51 Figure 4.13: Hspice option ................................................................................................. 52 Figure 4.15: Delay from clk rise to resetx rise ................................................................... 53 Figure 4.14: Cycle time must cover the internal clock ....................................................... 53 Figure 4.17: Delay from clk rise to dmrbl rise ................................................................... 54 Figure 4.16: Cycle time must make sure all RBL be precharged fully .............................. 54 Figure 4.18: Cycle time must cover PWH of input latch plus for max setup time ............ 55 Figure 4.19: PWH of input latch ........................................................................................ 55 Figure 4.20: Access time definition.................................................................................... 56 Figure 4.21:Access time ..................................................................................................... 56 Figure 4.22: Address input path delay ................................................................................ 57 Figure 4.23: Clock path delay ............................................................................................ 57 Figure 4.24: Delay from CLKA to intckx fall .................................................................... 58 Figure 4.25: Delay from intclk fall to rhcpx fall ................................................................ 58 Figure 4.26: Delay from rhcpx fall to latch rise ................................................................. 58 Figure 4. 27: Delay from rhcpx fall to echo rise ................................................................ 59 Figure 4.28: Delay from echo rise to resetx fall ................................................................. 59 Figure 4.29: Delay from resetx fall to intclk rise ............................................................... 59 Figure 4.30: delay from intclk rise to rhcpx rise ................................................................ 60 Figure 4.31: Delay from rhcpx rise to latch fall ................................................................. 60 Figure 4.32: Delay from intclk rise to resetx rise ............................................................... 60 Figure 4.33: Netlist of top level .......................................................................................... 66 Figure 4.34: A part of full test vector ................................................................................. 66 Figure 4.35: Hsim option .................................................................................................... 67 Figure 4.37: Waveform of SRAM functional simulation ................................................... 68 Figure 4.36: Hsim log file .................................................................................................. 68 Figure 4.38: Waveform of EDC functional simulation ...................................................... 69 Figure 4.39: LVS Calibre report for hierachical checking ................................................. 71 Figure 4.40: Detail LVS report for top level ...................................................................... 72 Figure 4.41: DRC report ....................................