Review ATA - IDE - Project: ATA – IDE Training - Minh Nguyen

Review ATA - IDE Project name : ATA – IDE Training Engineer : Minh Nguyen Interface register definition and descriptions • Device Control Register. • Device/Head Register. • Error Register. • Feature Register. • Sector Count Register. • Sector Number Register. • Status Register • Alternate Status Register. • Command Register. • Cylinder High Register. • Cylinder Low Register. • Data Register. Overview • ATA - Advanced Technology Attachment • IDE - Integrated Drive Electronics • PIO - Programmed Input/Output • DMA – Direct Memory Access • LBA – Logical Block Address • CFA – Compact Flash Association • CHS – Cylinder – Head – Sector • CRC – Cyclical Redundancy Check Interface register definition and descriptions •Reading this register shall not clear a pending interrupt. •This register contains the same information as the Status register in the command block. •Command processi g begins when this register is written. •The content of the Command Block registers become parameters of the command when this register is written. •This register contains the command code being sent to the device. Command execution begins immediately after this register is written. •This register shall only be written when DMACK- is not asserted. •The content of this register hall take effect when written. Interface register definition and descriptions Interface register definition and descriptions Bit BSY (Busy): • Set to one : (by device ) – Negation of RESET or SRTS(DC) = 1. – Written command register complete if DRD = 0. – During PIO data in/out >DRQ=>0. – During data transfer (DMA). – During the execution of a PACKET command .  Device : – Control Command Block Register.  Host : – Ignore write CCBR. – Read CCBR -> invalid, except bit BSY. Interface register definition and descriptions Bit BSY (Busy) : • Set to zero : (by device) – After DRQ = 0. – At command completion. – Overlapped command. – Device ready to accept command  Host has control of the Command Block register.  Device : – Not set DRQ -> 1. – Not change Error bit. – Not change the content Command Block register. – Set SERV->1. Interface register definition and descriptions DRDY (Device Ready): • Set to one : (by device) – Capable accept all command  Device : – Shall accept and to execution all command Interface register definition and descriptions DRQ (Data Request ): • Set to one : (by device ) – BSY = 1 and ready for PIO transfer. – During the data transfer of DMA command BSY and DRQ -> 1.  Host : – Transfer data via PIO mode – If DMARQ and DMACK -> A => DMA mode. • Set to zero : (by device ) – When the last word of the data/command packet transfer occurs.  Host : – Transfer data via DMA Interface register definition and descriptions ERR (Error) : • Set to one : (by device) – BSY or DRQ = 1 & an error occur. Bits in the Error register shall be valid. Device not change contain registers until new command, SRST -> 1, RESET -> A : Error, Cylinder High/Low, Sector Count/Number, Device/Head. • Set to zero : (by device) – When a new command is written to the Command register. – SRST -> 1. – RESET - > A.  Host : – Ignore contains of the Error register Command descriptions • DEVICE RESET – Input : – Output : Command descriptions • Identify device : – Inputs : – Outputs : Command descriptions • Read DMA : – Inputs: – Outputs: Command descriptions • Read DMA : Command descriptions • Read Multiple : – Inputs: – Outputs: Command descriptions • Read Multiple : – Error outputs: Command descriptions • Read Sector : – Inputs : – Outputs: Command descriptions • Read Sector : – Error outputs: Command descriptions • Set Features : – Inputs: – Error outputs: Command descriptions • Set multiple mode : – Inputs : – Outputs : The host shall set Sector Count values equal to 2, 4, 8, 16, 32, 64, or 128. Command descriptions • Set multiple mode : – Error outputs : Command descriptions • Write DMA : – Inputs : – Outputs : Command descriptions • Write DMA : – Error outputs : Command descriptions Write multiple & write sector : Command descriptions • Write multiple : – Inputs : – Outputs : – Error outputs : Command descriptions • Write sector : – Inputs : – Outputs : Command descriptions • Write sector : – Error outputs : Protocol • PIO protocol. – PIO data in command protocol – PIO data out command protocol • DMA protocol • Ultra DMA Protocol – Ultra protocol data in burst – Ultra protocol data out burst PIO Protocol •  data transfer are performed by host processor utilizing PIO register access to data register – Read/write multiple – Read/write sector DMA Protocol •  data transfer between device and host memory without host processor intervention. •  data transfer are performed using DMA channel. •  a single interrupt issued at command completion. Ultra DMA Protocol •  data transfer from assertion DMACK to the subsequent negation DMACK. •  Phase of operation : – Initiation phase – Data transfer phase – Termination phase