Review PCI – CMD649 - Project: Linux Training - Minh Nguyen Van

Review PCI – CMD649 Project : Linux Training Engineer : Minh Nguyen Van PCI Configuration Register • Header Type PCI Configuration Register • Vendor ID  manufacture of device • Device ID  type of device • Subsystem Vendor ID and Subsystem ID Register :  the OS distinguish the difference between cards or subsystems.  These two registers must contain their assigned values before the system first accesses them PCI Configuration Register • Revision ID Register : Identifies revision number of the device • Base Address Register : PCI Configuration Register • Base Address Register Bits [2:1] : 00b => 32 bit register 10b => 64 bit register PCI Configuration Register • Class Code Register : PCI Configuration Register • Command Register PCI Configuration Register • Status Register CMD 649 Features • 2 independent IDE/ATA Channels • Supports ultra and multiword DMA timing modes • Built in 80-Pin cable detect circuitry • Supports External BIOS • 32-bit 33 MHz PCI Interface • Supports bus master DMA at 133 MB/sec PCI burst rate • Supports maximum IDE/ATA data transfer rate of 100 MB/sec CMD 649 • PCI Interface – When the PCI- 649 needs to access shared memory, it becomes the bus master of the PCI bus and completes the memory cycle without external intervention. – In the mode when it acts as a bridge between the PCI bus and the IDE/ATA bus it will behave as a PCI slave. CMD 649 Setup transfer PIO • CMDTIM (0x52h) • ARTTIMx (0x53h – 0x55h – 0x57h) • DRWTIMx (0x54h – 0x56h – 0x58h – 0x5Bh) • UDIDETCRx(0x73h – 0x7Bh) Bits 0 & 1 = 0 (PIO) Bits 0 & 1 = 1 (UDMA) CMD 649 – Setup PIO • IDE/ATA Task File Timing Control Register (CMDTIM) •  upper 4 bits represent active time • lower 4 bits represent recovery time • Drive x Address Setup Register (ARTTIMx) for PIO modes •  the variable “x” in registers the drive number •  bits [6,7] Address set up time – 00  4 clocks (120ns) – 01  2 clocks (60ns) – 10  3 clocks (Default, 90ns) – 11  5 clocks (150ns) CMD 649 • Drive x DIOR/DIOW or DACK Timing Register (DRWTIMx) for PIO/MDMA Modes •  upper 4 bits represent active time – 0000  16 clocks, 0001  1 clock, , 1111  15 clocks • lower 4 bits represent recovery time – 0000  16 clocks, 0001  2 clocks, , 1111  1 clock • Ex : PIO4 : active time = 70ns, recovery time = 25 ns •  register : 0x3Fh(00111111) MDMA0 : active time = 215ns, recovery time = 265ns • register : 0x88h(10001000) Timing table CMD 649 – Setup UDMA • Channel x in Ultra DMA IDE/ATA Timing Control Registers (UDIDETCRx) • The two registers are UDIDETCR0 for primary channel and UIDETCR1 for secondary channel. • Bits [0,1]  1 • Bits [2,3] depending UDMA mode (1 for 3,4,5 and 0 for 0,1,2) • Ex : Master drive UDMA2 – Bit 2  0, bits[4,5]  [01] Flowchart