Review PCI Express, SATA II and Silicon image 3132 (SI3132) – CMD649 - Hoa Hoang

Review PCI Express, SATA II and Silicon image 3132 (SI3132) • Introduction PCI Express and SATA II • Silicon image 3132 Engineer: HOA HOANG Introduction PCI express • PCI Express is the third generation high performance I/O bus used to interconnect peripheral devices in applications. The first generation buses include the ISA, EISA, VESA, and Micro Channel buses, second generation buses include PCI, AGP, and PCI-X. Bus Type Specification Release Date of Release PCI 33 MHz 2.0 1993 PCI 66 MHz 2.1 1995 PCI-X 66 MHz and 133 MHz 1.0 1999 PCI-X 266 MHz and 533 MHz 2.0 Q1, 2002 PCI Express 1.0 Q2, 2002 Table 1-1. Bus Specifications and Release Dates Bus Type Clock Frequency Peak Bandwidth [*] Number of Card Slots per Bus PCI 32-bit 33 MHz 133 MBytes/sec 4-5 PCI 32-bit 66 MHz 266 MBytes/sec 1-2 PCI-X 32-bit 66 MHz 266 MBytes/sec 4 PCI-X 32-bit 133 MHz 533 MBytes/sec 1-2 PCI-X 32-bit 266 MHz effective 1066 MBytes/sec 1 PCI-X 32-bit 533 MHz effective 2131 MByte/sec 1 Introduction PCI express Table 1-2. Comparison of Bus Frequency, Bandwidth and Number of Slots Bus Type Clock Frequency Peak Bandwidth [*] Number of Card Slots per Bus PCI 32-bit 33 MHz 133 MBytes/sec 4-5 PCI 32-bit 66 MHz 266 MBytes/sec 1-2 PCI-X 32-bit 66 MHz 266 MBytes/sec 4 PCI-X 32-bit 133 MHz 533 MBytes/sec 1-2 PCI-X 32-bit 266 MHz effective 1066 MBytes/sec 1 PCI-X 32-bit 533 MHz effective 2131 MByte/sec 1 Introduction PCI express Table 1-2. Comparison of Bus Frequency, Bandwidth and Number of Slots PCI Express Aggregate Throughput Introduction PCI express A PCI Express interconnect that connects two devices together is referred to as a Link. A Link consists of either x1, x2, x4, x8, x12, x16 or x32 signal pairs in each direction. These signals are referred to as Lanes. Aggregate bandwith numbers in Table 1-3 multiply 2.5 Gbits/sec by 2 (for each direction) PCI Express Link Width x1 x2 x4 x8 x12 x16 x32 Aggregate Bandwidth (GBytes/sec) 0.5 1 2 4 6 8 16 Table 1-3. PCI Express Aggregate Throughput for Various Link Widths Introduction PCI express Some system PCI express in PC Low Cost PCI Express High-End Server System Definition of Device and Function Introduction PCI express  Device PCI may contain up to a maximum of eight functions numbered 0-through-7.  Each function's configuration space is 4KB in size and is populated as described in the following two subsections: + The 256 byte (64 dword) PCI-compatible space occupies the first 256 bytes of this 4KB space. + The remaining 3840 byte (960 dword) area is referred to as the PCI Express Extended Configuration Space. It is utilized to implement the optional PCI Express Extended Capability registers: Error Reporting, Virtual Channel, Device Serial Number, Power Budgeting. Introduction PCI express PCI- compatible space PCI Express Extended Configuration Space Introduction PCI express PCI-Compatible Configuration Mechanism Description  PCI-Compatible Configuration Mechanism use two 32-bit IO ports in Root Complex, located at IO addresses 0CF8h and 0CFCh. These two ports are: the 32-bit Configuration Address Port, IO addresses 0CF8h through 0CFBh and the 32-bit Configuration Data Port, IO addresses 0CFCh through 0CFFh.  Accessing one of a function's PCI configuration registers is a two step process: + Write the target bus number, device number, function number anddword number to the Configuration Address Port and set the Enable bit in it to one. + Perform a one-byte, two-byte, or four-byte IO read from or a write to the Configuration Data Port. Sample to access: mov dx,0CF8 ;set dx = config address port address 0CF8 mov eax,80040000 ;enable=1, bus 4, dev 0, Func 0, select Dword 00 out dx,eax ;write to address port mov dx,0CFC ; set dx = config data port address in ax,dx ;2 byte read from Differentiate between PCI-to-PCI Bridge and Non-Bridge Function. Introduction PCI express Header Type: 0 = the function is not a bridge. 1 = the function is a PCI-to-PCI bridge. 2 = the function is a CardBus bridge. Introduction PCI express Header Type: Type 0 Type 1 Registers Used to Identify Device's Driver by OS and driver Introduction PCI express The OS uses some combination of the following mandatory registers to determine which driver to load for a device: - Vendor ID: Always mandatory. Identifies the manufacture - Device ID: Always mandatory. type of function. - Revision ID: Always mandatory. 8-bit . It use for ensuring that the correct driver is loaded by OS. - Class Code: 24 bit, divided into three fields: base Class, Sub Class, and Programming Interface. It identifies the basic function of the function (e.g., a mass storage controller), a more specific function sub-class (e.g., IDE mass storage controller), and, in some cases, a register-specific programming interface (such as a specific flavor of the IDE register set). - SubSystem Vendor ID and SubSystem ID.: This excludes bridges of the following types: Host/PCI: 00h; PCI-to-EISA: 02h; PCI-to-ISA : 01h; PCI-to- Micro Channel: 03h;PCI-to-PCI: 06h Introduction PCI express Base Address Registers If bit 0 = 0, the register is a memory address decoder If bit 0 = 1, the register is an IO address decoder. Bits [2:1] define whether the decoder is 32- or 64-bits wide Introduction PCI express Interrupt Line Register: Values 00h-through-0Fh in this register correspond to the IRQ0-through-IRQ15 inputs on the interrupt controller. Values from 10h-through-FEh are reserved. Values FFh is indicated “unknown” or “no connection”. Interrupt Pin Register: (read only) The values 01h-through-04h correspond to PCI interrupt request pins INTA#-through-INTD#. A return value of zero indicates that the device doesn't generate interrupts. All other values (05h-FFh) are reserved. Serial ATA II port multiplier Serial ATA II port multipliers attach up to 15 devices to a host – Stores and forwards frames from the host based on a field in the frame header – Fills in that field for frames from devices Sata II Frame Information Structure (FIS) Sata II FIS is a group of Dwords that convey information between host and device FIS Types Sata II Status and Control Registers: Serial ATA provides an additional block of registers to control the interface and to retrieve interface state information. SCR table SStatus register: DET The DET value indicates the interface device detection and Phy state. Value Description 0000b No device attached 0001b Device attached 0011b Device attached and running 0100b Phy is disabled or in loopback mode other values Reserved SPD: report speed being used Value Description 0 No device attached 1 1.5 Gbps 2 3.0 Gbps 3 to 15 Reserved IPM (interface power management) field reports the power management state of the phy. Value Description 0 No Device attached 1 Active state 2 Partial power management state 3 Slumber power management state 4 to 15 Reserved Note : The interface needs to be in the active state. Sata II SError register: SControl register: Sata II SILICON IMAGE 3132 (SI3132) SILICON IMAGE 3132 (SI3132) Device ID – Vendor ID Type: Read /Write Reset value : 0x3132_1095 Use by driver to identify silicon Image 3132 Max Latency – Min Grant – Interrupt Pin – Interrupt Line Access Type: Read/Write Reset Value: 0x0000_0100 Interrupt Pin (R) – Interrupt Pin Used. This bit field is hardwired to 01H to indicate that the SiI3132 uses the INTA interrupt. Interrupt Line (R/W) – Interrupt Line. This bit field is used by the system to indicate interrupt line routing information. Internal Register Space – Base Address 0 SILICON IMAGE 3132 (SI3132) Access to this register space is through the PCI Memory space. Port Slot Status Registers Access Type: Read Reset Value: 0x0000_0000 Bit [31]: Attention (R) – This bit indicates that something occurred in the corresponding port that requires the attention of the host. The host will read other register to identify error. Bit[30->1] These bits indicates slot number from 0 to 30 when Command Execution FIFO (direct command transfer method) or when a Command Activation register is written (indirect command transfer method). Global Control Access Type: Read/Write Reset Value: 0x8100_0000 SILICON IMAGE 3132 (SI3132) Bit [31]: Global Reset (R/W). This bit when set to one will reset all port (port 0 and port 1). • Bit [30]: MSI Acknowledge (W). Writing a one to this bit acknowledges a Message Signaled Interrupt and permits generation of another MSI. • Bit [29]: I2C Int Enable (R/W). This bit, when set to one, allows assertion of an interrupt when the I2C interrupt is asserted. • Bit [28:25,23:2]: Reserved (R). • Bit [24]: 3Gb/s Capable (R). This bit is hardwired to one. • Bit [1:0]: Port Interrupt Enable (R/W). port 0 and port 1. Global Interrupt Status Access Type: Read/Write 1 Clear Reset Value: 0x0000_0000 Bit [1:0]: Port Interrupt Status (R/W1C). These bits, when set to one, indicate port has an interrupt condition pending. SILICON IMAGE 3132 (SI3132) Port LRAM Access Type: Read/Write Reset Value: indeterminate SILICON IMAGE 3132 (SI3132) A Port LRAM Slot is 128 bytes used to define Serial-ATA commands. The addresses shown above are for slot 0. Port Slot Status Access Type: Read Reset Value: 0x0000_0000 Bit 31: Attention : indicate port has error. Bit [30:0]: Slot Status (R) – These bits are the Active status bits corresponding to Slot numbers 30 to 0. SILICON IMAGE 3132 (SI3132) Port Control Set Access Type: Write One To Set Reset Value: N/A Bit [10]: 32-bit Activation Bit [13]: PM Enable (W1S). This bit enables Port Multiplier support. Bit [3]: Interrupt No Clear on Read (W1S). When this bit is set to one, a command completion interrupt may be cleared only by writing a one to the Command Completion bit in the Port Interrupt Status register. Bit [1]: Device Reset (W1S) Bit [0]: Port Reset (W1S) Port Status Access Type: Read Reset Value: 0x001F_0001 Port Control Clear SILICON IMAGE 3132 (SI3132) Address Offset: 1004H Access Type: Write One To Clear Reset Value: N/A Port Interrupt Status Access Type: Read/Write 1 Clear Reset Value: 0x0000_0000 This image cannot currently be displayed. This register will contain information of interrupt port . SILICON IMAGE 3132 (SI3132) Port Interrupt Enable Set / Port Interrupt Enable Clear Address Offset: 1010H / 1014H Access Type: Read/Write 1 Set/Write 1 Clear Reset Value: 0x0000_0000 This image cannot currently be displayed. Bit [31:30]: Interrupt Steering (R/W). specifies one of 4 interrupts use for this port Interrupt INTA INTB INTC INTD Value 00 01 10 11 Bit [11,7:0]: Interrupt Enables (R/W1S/W1C). These bits enable many source difference interrupt. Port Command Execution FIFO Access Type: Read/Write Reset Value: 0x0000_00XX This register use for method direct command (PRB). After software write commands to slot Ram(0 to 30), the software will write slot number to this register. SILICON IMAGE 3132 (SI3132) Port Command Error Access Type: Read Reset Value: 0x0000_0000 This register contains the error type resulting from a command error. It is important for software to identify command error code when interrupt error command enable. See table below: SILICON IMAGE 3132 (SI3132) Error name code Description DEVICEERROR 1 Bit err was set SDBERROR 2 Bit err was set DATAFISERROR 3 The SiI3132 detected an error. SENDFISERROR 4 The SiI3132 was unable to send the Initial command FIS for a command. INCONSISTENTSTATE 5 The SiI3132 detected an inconsistency (trai nguoc) in protocol. DIRECTIONERROR 6 Direction error (A Data FIS and command code opposite) UNDERRUNERROR 7 While transfer data from SI3132 to device, the SGE end. OVERRUNERROR 8 While transfer data from device to SI3132, Not enough space in SGE PACKETPROTOCOLERROR 11 During the first PIO setup of Packet command, the data direction bit was invalid, indicating a transfer from device to host. SControl Access Type: Read/Write Reset Value: 0x0000_0000 This register is defined by Sata spec. PMP: This field identifies the currently selected Port Multiplier port. SPM: This field selects a power management state for device. Value Definition 0000 No power management state transition requested 0001 Transition to the Partial power management state initiated 0010 Transition to the Slumber power management state initiated 0100 Transition from a power management state initiated (ComWake asserted) others Reserved SILICON IMAGE 3132 (SI3132) Partial and Slumber power mode is stanby mode when device or host adapter not active (auto change mode). SPD (R) – This field identifies the negotiated interface communication speed. Value Definition 0000 No negotiated speed 0001 Generation 1 communication rate (1.5 Gbit/s) 0010 Generation 2 communication rate (3.0 Gbit/s) Others Reserved SILICON IMAGE 3132 (SI3132) DET (R) – This field indicates the interface device detection and PHY state Value Action 0000 No device detected and PHY communication not established 0001 Device presence detected but PHY communication not established 0011 Device presence detected and PHY communication established 0100 PHY in offline mode as a result of the interface being disabled or running in a BIST loopback mode Others Reserved, no action SStatus Access Type: Read Reset Value: 0x0000_0000 SError Access Type: Read/Write 1 Clear Reset Value: 0x0000_0000 SILICON IMAGE 3132 (SI3132) SILICON IMAGE 3132 (SI3132) Prepare PRB The PRB contains two SGEs Prepare The Scatter/Gather Entry (SGE) Data Address Low Data Address High Data Count TRM (31) LNK (30) DRD (29) XCF (28) Reserved[27:0] 0x00 0x04 0x08 0x0C Data Address Low, Data Address High : contain the physical address of region memory host. In the platform 32bit Data address high = 0. Data address use for transfer data between host and device. LNK(30): this bit define type of region. LNK =0: this is Data region. LNK = 1: this is the address region. Data count : define the length in byte. When LNK = 1, data count is ignored. TRM : when this set to one. It indicates this is the final SGE. DRD : when this bit set to one. It XCF: when XCF = 0 It indicates this SGE is used transfer data. XCF =1 this is command fetch(link). The Scatter/Gather Table (SGT) The SGT is simply a contiguous collection of four SGE. Prepare The Port Request Block (PRB) PRB define command that use by SI3132 to send command to device(SATA disk). PBR contain 64 bytes. The PRB contains the following major elements: A Control Field to indicate the type of PRB and any features to execute. For SATA command standard it will normally contain a default value of 0x0000. The Protocol Override Field (offset 0x00, bits [31:16]) is used to specify a protocol other than the default for this PRB. PRB should use protocol default is 0x0000. A FIS area that contains the initial FIS to be transmitted to the device upon PRB execution. Two Scatter/Gather entries (SGEs) to define areas of host memory that will be used for any data transfer associated with the PRB. SILICON IMAGE 3132 (SI3132) Standard ATA Command PRB Structure Protocol Override Control Received Transfer Count Features / Error Command / Status C R R R PMP FIS Type Dev/Head Cyl High Cyl Low Sector Number 70 Features (Exp) Cyl High (Exp) Cyl Low (Exp) Sector Num (Exp) Device Control Reserved Sector Count (Exp) Sector Count Reserved Reserved Reserved Reserved Reserved – Must Be Zero SGE0 Data Address Low SGE0 Data Address High SGE0 Data Count SILICON IMAGE 3132 (SI3132) 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C SGE0 TRM SGE0 LNK SGE0 DRD SGE0 XCF Reserved[27:0] SGE1 Data Address Low SGE1 Data Address High SGE1 Data Count SGE1 TRM SGE1 LNK SGE1 DRD SGE1 XCF Reserved[27:0] SILICON IMAGE 3132 (SI3132) Software reset PRB struct N/A Control (0x0080) N/A Features / Error Command / Status C R R R PMP FIS Type Dev/Head Cyl High Cyl Low Sector Number Features (Exp) Cyl High (Exp) Cyl Low (Exp) Sector Num (Exp) Device Control Reserved Sector Count (Exp) Sector Count N/A 0X00h 0X04h 0X08h 0X00h 0X0Ch 0X00h 0x18h 0X3C Software reset sequence to the device and wait for a “Register – Device to Host” FIS to deliver the device signature and terminate the command. Soft read device signaturerom the command slot to determind SILICON IMAGE 3132 (SI3132) Command Issuance a. Indirect Command b. Direct Command Start Build PRB table, prepair memory region Write PRB table in slot (0->30) Ram( map to base address 1) Write the number of slot into command execution FIFO register end Start Build PRB table, prepair memory region Write physical address of PRB to command activation register end Direct Command Indirect Command SILICON IMAGE 3132 (SI3132) Main issue command Initialization Sequence Thank You!